1. Technical Field
Various embodiments generally relate to a semiconductor device, and more particularly, to a technology for controlling ZQ calibration of a semiconductor device including two dies configured as a single chip.
2. Related Art
Developments are being made to increase the degree of integration and the operating speeds of semiconductor memory devices. Synchronous memory devices have been developed to increase the operating speeds of the semiconductor memory devices. These synchronous memory devices are capable of operating in synchronization with a clock signal received from outside a memory chip.
For example, an SDR (single data rate) synchronous memory device may be implemented whereby data is inputted and outputted through a single data pin during a single clock cycle. In the SDR synchronous memory device, the input and output of the data is in synchronization with the rising edge of a clock signal.
However, the SDR synchronous memory device has difficulty in operating with systems requiring high speed operations. Accordingly, a DDR (double data rate) synchronous memory device may be implemented whereby data is consecutively inputted and outputted through each data input/output pin, in synchronization with the rising edge and the falling edge of a clock signal.
As such, a bandwidth at least two times wider than the conventional SDR synchronous memory device may be realized without increasing the frequency of a clock signal, and thus, a high speed operation may be achieved.
A semiconductor device is being designed in a direction for consuming less power, and a data pattern information signal is used by being defined by a specification.
In particular, a memory for a high speed operation is being designed to be capable of receiving addresses at not only the rising edge but also the falling edge of an external clock. Since it is possible to receive addresses two times for one cycle, the number of address pins may be decreased when compared to a conventional semiconductor memory device. Also, an extra number of pins may be connected with a power supply voltage or a ground voltage to increase the operation speed of the semiconductor memory device.
In a semiconductor memory device such as a dynamic random access memory (DRAM), in order to achieve a larger capacity from a unit area, a plurality of semiconductor chips (or dies) are stacked and then packaged.
A semiconductor memory device packaged with only one semiconductor chip may be referred to as a single die package (SDP). Also, a semiconductor memory device stacked and packaged with two semiconductor chips may be referred to as a dual die package (DDP). Further, a semiconductor memory device stacked and packaged with four semiconductor chips may be referred to as a quad die package (QDP).
A low voltage semiconductor device (for example, an LPDDR4) is internally configured by 2 channels and is realized by mirroring two of the same chips in one die. In the case where only one channel is realized in one die for variety of business or actual maximization of a net die, two dies should be electrically coupled at a package level.
Originally, in 1 chip of a low voltage semiconductor device, only one ZQ pin exists for 2 channels.